Part of the EDA team which is responsible for developing an HDL front-end compiler that checks whether given designs obey a given industry standard (e.g. GB/T 37979-2019 standard for VHDL).
Established mappings among stages from source code to netlists to enable back-tracing of logic synthesis.
Implemented VHDL code style checking rules based on GB/T 37979-2019 standard.